What are you using to make your VHDL development faster and cleaner; eMacs configurations files / linters etc.

  • beemer2001ny@communick.newsOP
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    1 year ago

    Currently, i’m using the following packages, still a work in progress and looking for how you are using it differently.

    • all-the-icons
    (use-package all-the-icons
      :ensure t)
    
    • company
    (use-package company
      :ensure t         
      :hook ((vhdl-mode . company-mode)   
             (after-init . global-company-mode))
      :custom
      (company-idle-delay 0))  
    
    • flycheck
    (use-package flycheck
      :ensure t
      :hook (vhdl-mode . flycheck-mode)
      :config
      ;; Specify the VHDL language standard for GHDL (you can change the standard as needed)
      (setq flycheck-ghdl-language-standard "08")
      ;; If you need to specify a work directory for GHDL, you can set it like this:
      (setq flycheck-ghdl-workdir "/usr/bin/ghdl/")
    )
    
    • magit
    (use-package magit
      :commands (magit-status magit-get-current-branch)
      :custom
      (magit-display-buffer-function #'magit-display-buffer-same-window-except-diff-v1))
    
    • marginalia
    (use-package marginalia
      :after vertico
      :ensure t
      :init
      (marginalia-mode))
    
    • projectile
    (use-package projectile
      :config
      (projectile-mode 1))
    
    • rainbow-delimiters
    (use-package rainbow-delimiters
      :hook (prog-mode . rainbow-delimiters-mode))
    
    • savehist
    (use-package savehist
      :init
      (savehist-mode))
    
    • spaceemacs-theme
    (use-package spacemacs-theme
      :ensure t
      :defer t
      :init
      (load-theme 'spacemacs-dark t))
    
    • verilog-mode
    (use-package verilog-mode
      :mode ("\\.v\\'" . verilog-mode)
            ("\\.sv\\'" . verilog-mode)
      :config
      (setq verilog-indent-level 4
            verilog-indent-level-module 4
            verilog-indent-level-declaration 4
            verilog-indent-level-behavioral 4
            verilog-indent-level-directive 2)
      ;; Verible as linter for Verilog
      (flycheck-define-checker verilog-verible
        :command ("verible-verilog-lint" source)
        :error-patterns
        ((warning line-start (file-name) ":" line ": " (message) line-end))
        :modes verilog-mode)
      (add-to-list 'flycheck-checkers 'verilog-verible))
    
    • vertico
    (use-package vertico
      :ensure t
      :custom
      (vertico-cycle t)
      (read-buffer-completion-ignore-case t)
      (read-file-name-completion-ignore-case t)
      (completion-styles '(basic substring partial-completion flex))
      :init
      (vertico-mode))
    
    • vhdl-mode
    (use-package vhdl-mode
      :ensure t
      :mode ("\\.vhdl?\\'" . vhdl-mode)
            ("\\.vhd?\\'" . vhdl-mode)
      :bind (:map vhdl-mode-map
                  ("S-" . vhdl-speedbar))
      :config
      (setq vhdl-speedbar-update-on-saving t
            vhdl-clock-name "i_clk"
            vhdl-clock-rising-edge t
            vhdl-clock-edge-condition 'function
            ;; RESET
            vhdl-reset-kind 'sync
            vhdl-reset-name "i_rst"
            vhdl-reset-active-high t
            ;; COMMENTS
            vhdl-self-insert-comments nil
            vhdl-include-port-comments nil
            vhdl-include-direction-comments nil
            vhdl-include-type-comments nil
            vhdl-include-group-comments 'always
            vhdl-end-comment-column 80
            vhdl-inline-comment-column 20
            vhdl-comment-inline-offset 2
            vhdl-comment-empty-lines t
            ;; GENERAL
            vhdl-standard '(93 nil)
            vhdl-indent-tabs-mode nil
            vhdl-basic-offset 4
            vhdl-electric-mode t
    	 vhdl-stutter-mode t
            vhdl-index-menu t
            vhdl-source-file-menu t
            vhdl-insert-empty-lines nil
            vhdl-upper-case-keywords nil
            vhdl-upper-case-types nil
            vhdl-upper-case-attributes nil
            vhdl-upper-case-enum-values nil
            vhdl-highlight-case-sensitive nil
            vhdl-highlight-translate-off nil
            vhdl-word-completion-case-sensitive nil
            vhdl-underscore-is-part-of-word t
            vhdl-align-groups nil
            vhdl-fixup-whitespace-region t
            vhdl-conditions-in-parenthesis t
            vhdl-optional-labels 'process
            ;; PORT MAPS
            vhdl-actual-port-name '(".*" . "\\&")
            ;; INSTANCE
            vhdl-instance-name '(".*" . "u_\\& ")
            vhdl-component-instance t)
    
      ;;============================================================================
      ;; help provided by steve9232
      (defun my-vhdl-mode-hook ()
      (vhdl-set-offset 'arglist-close 0))
      (add-hook 'vhdl-mode-hook 'my-vhdl-mode-hook)
    
      ;;============================================================================
      ;; compile rtl  
      (defun vhdl-compile-with-ghdl ()
        "Compile the current VHDL file using GHDL."
        (interactive)
        (let ((compile-command (concat "ghdl -a " buffer-file-name)))
          (compile compile-command)))
    
      (defun vhdl-compile-run-with-ghdl ()
        "Compile and run the current VHDL file using GHDL."
        (interactive)
        (vhdl-compile-with-ghdl)
        (let ((run-command (concat "ghdl -r " (file-name-sans-extension buffer-file-name))))
          (compile run-command)))
    
      :hook
      (vhdl-mode . (lambda ()
                     (local-set-key (kbd "C-c C-c") 'vhdl-compile-with-ghdl)
                     (local-set-key (kbd "C-c C-r") 'vhdl-compile-run-with-ghdl))))
    
    • which-key
    (use-package which-key
      :ensure t
      :config
      (which-key-mode))
    
    • yasnippet
    (use-package yasnippet
      :ensure t
      :config
      (yas-global-mode 1))
      ;;:config
      ;;(yas-load-directory "~/.emacs.d/snippets/")